1. Field of the Invention
The present invention relates to a demodulation circuit, a demodulation method, a program, and a reception apparatus. In particular, the present invention relates to a demodulation circuit, a demodulation method, a program, and a reception apparatus which make it possible to stabilize an operation of an equalizer even when there are variations in a channel.
2. Description of the Related Art
In terrestrial digital broadcasting, the amplitude and phase of a signal may differ between transmission and reception due to influence of multipath and so on during transmission. Therefore, a receiver needs to perform equalization on the signal at the time of demodulation, so that the signal received will be identical in amplitude and phase to the signal transmitted.
FIG. 1 illustrates an exemplary structure of an equalizer 1 provided in a known digital demodulation apparatus (a demodulation circuit).
As illustrated in FIG. 1, the equalizer 1, which is formed by a decision feedback equalizer (DFE), i.e., one method of constructing an equalizer, includes a feed forward equalizer (FFE) 11 and a feed back equalizer (FBE) 14. A signal that is outputted from a unit that performs a synchronization process and provided in a stage previous to the equalizer 1 is inputted to the FFE 11.
The FFE 11 is composed of a finite impulse response (FIR) filter and so on. The FFE 11 subjects the input signal into filtering based on a filter coefficient set by a coefficient update section 16. The resulting signal, obtained from the filtering by the FFE 11, is inputted to an adding circuit 12.
The adding circuit 12 adds the signal supplied from the FFE 11 to a signal supplied from the FBE 14, and outputs the resulting signal as a post-equalization signal. The post-equalization signal outputted from the adding circuit 12 is supplied to an error correction processor or the like that is provided in a stage subsequent to the equalizer 1, and is also inputted to a slicer 13, a blind error calculation section 21, and a decision-directed (DD) error calculation section 22.
The slicer 13 calculates a hard decision value for the post-equalization signal supplied from the adding circuit 12. In the slicer 13, based on a value, e.g., 1.5, which is represented by the post-equalization signal, the hard decision value, e.g., 1, which is close to that value, is obtained. A signal representing the hard decision value obtained by the slicer 13 is inputted to the FBE 14 and the DD error calculation section 22.
The FBE 14 is also composed of the FIR filter and so on, and subjects the signal representing the hard decision value obtained by the slicer 13 to filtering based on a filter coefficient set by the coefficient update section 16. The resulting signal, obtained from the filtering by the FBE 14, is inputted to the adding circuit 12, and used, in combination with the signal outputted from the FFE 11, to generate the post-equalization signal.
An error calculation block 15 includes the blind error calculation section 21, the DD error calculation section 22, and a selector 23.
The blind error calculation section 21 calculates an error in the post-equalization signal supplied from the adding circuit 12 in accordance with a blind method. Here, equalization that is performed while updating the filter coefficients in such a direction that the error calculated in accordance with the blind method will decrease is referred to as blind equalization. The blind equalization makes it possible to reproduce a transmitted signal by estimating an inverse characteristic of a channel based on a received signal, while characteristics of the channel and input are unknown. In the blind error calculation section 21, the error is calculated based on an equation defined by a modulation scheme and the value represented by the post-equalization signal supplied from the adding circuit 12. A signal that represents the error (i.e., a blind error) calculated by the blind error calculation section 21 is inputted to the selector 23.
The DD error calculation section 22 calculates an error in the post-equalization signal in accordance with a DD method, based on the post-equalization signal supplied from the adding circuit 12 and the signal representing the hard decision value supplied from the slicer 13. In the case where the value represented by the post-equalization signal supplied from the adding circuit 12 is 1.5 as described above, and the hard decision value represented by the signal supplied from the slicer 13 is 1, for example, the DD error calculation section 22 obtains a difference between the two values, 0.5, as the error in the post-equalization signal. A signal that represents the error (i.e., a DD error) calculated by the DD error calculation section 22 is inputted to the selector 23.
The selector 23 selects one of the signal representing the blind error supplied from the blind error calculation section 21 and the signal representing the DD error supplied from the DD error calculation section 22, and outputs the selected signal to the coefficient update section 16.
The coefficient update section 16 updates the filter coefficient for the FFE 11 and the filter coefficient for the FBE 14, based on the error represented by the signal supplied from the selector 23. The coefficient update section 16 updates the filter coefficients in such a direction that the error in the post-equalization signal will decrease.
Japanese Patent Laid-open No. 2002-33682 discloses a technique of estimating an equalizer output based on a minimum entropy method and adjusting an equalizer parameter in such a manner as to optimize the equalizer output.